? semiconductor components industries, llc, 2001 april, 2001 rev. 1 1 publication order number: mc74vhct139a/d mc74vhct139a product preview dual 2-to-4 decoder/ demultiplexer the mc74vhct139a is an advanced high speed cmos 2to4 decoder/ demultiplexer fabricated with silicon gate cmos technology. it achieves high speed operation similar to equivalent bipolar schottky ttl devices while maintaining cmos low power dissipation. when the device is enabled (e = low), it can be used for gating or as a data input for demultiplexing operations. when the enable input is held high, all four outputs are fixed high, independent of other inputs. the internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. the device output is compatible with ttltype input thresholds and the output has a full 5 v cmos level output swing. the input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logiclevel translator from 3.0 v cmos logic to 5.0 v cmos logic, or from 1.8 v cmos logic to 3.0 v cmos logic while operating at the highvoltage power supply the mc74vhct139a input structure provides protection when voltages up to 7 v are applied, regardless of the supply voltage. this allows the mc74vhct139a to be used to interface 5 v circuits to 3 v circuits. the output structures also provide protection when v cc = 0 v. these input and output structures help prevent device destruction caused by supply voltageeinput/output voltage mismatch, battery backup, hot insertion, etc. ? high speed: t pd = 5.0ns (typ) at v cc = 5v ? low power dissipation: i cc = 4 ma (max) at t a = 25 c ? ttlcompatible inputs: v il = 0.8 v; v ih = 2.0 v ? power down protection provided on inputs and outputs ? balanced propagation delays ? designed for 2v to 5.5v operating range ? low noise: v olp = 0.8 v (max) ? pin and function compatible with other standard logic families ? latchup performance exceeds 300ma ? esd performance: hbm > 2000v; machine model > 200v ? chip complexity: 100 fets or 25 equivalent gates figure 1. pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 ea a1a a0a gnd a1b a0b eb v cc y0a y1a y2a y3a y0b y1b y2b y3b http://onsemi.com soic16 d suffix case 751b marking diagrams 1 8 9 16 1 8 16 9 1 16 9 8 vhct139a awlyyww a = assembly location l, wl = wafer lot y, yy = year w, ww = work week vhct139a awlyww vhct139a alyw tssop16 dt suffix case 948f soic eiaj16 m suffix case 966 device package shipping ordering information mc74vhct139ad soic16 48 units/rail mc74vhct139adr2 soic16 2500 units/reel mc74vhct139adt tssop16 96 units/rail tssop16 2000 units/reel mc74vhct139am soic eiaj16 48 units/rail mc74vhct139amel soic eiaj16 2000 units/reel mc74vhct139adtr2
mc74vhct139a http://onsemi.com 2 figure 2. logic diagram a0a a1a ea a0b a1b 1 eb y0a y1a y2a y3a y0b y1b y2b y3b active-low outputs address inputs active-low outputs 3 2 address inputs 13 14 15 4 5 6 7 12 11 10 9 function table inputs outputs e a1 a0 y0 y1 y2 y3 hxxhhhh llllhhh llhhlhh lhlhhlh lhhhhhl en a0 a1 y0 y1 y2 y3 figure 3. expanded logic diagram (1/2 of device) input figure 4. input equivalent circuit 4 figure 5. iec logic diagram y0a y1a y2a y3a y0b y1b y2b y3b 5 6 7 12 11 10 9 15 14 13 1 2 3 a1a a0a ea a1b a0b eb 2 1 en x/y 1 0 2 3 0 1 dmux 1 0 2 3 g 0 3 15 14 13 1 2 3 a1a a0a ea a1b a0b eb y0a y1a y2a y3a y0b y1b y2b y3b 4 5 6 7 12 11 10 9
mc74vhct139a http://onsemi.com 3 maximum ratings (note 1.) symbol parameter value unit v cc positive dc supply voltage 0.5 to +7.0 v v in digital input voltage 0.5 to +7.0 v v out dc output voltage output in 3state high or low state 0.5 to +7.0 0.5 to v cc +0.5 v i ik input diode current 20 ma i ok output diode current 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 75 ma p d power dissipation in still air soic package tssop 200 180 mw t stg storage temperature range 65 to +150 c v esd esd withstand voltage human body model (note 2.) machine model (note 3.) charged device model (note 4.) >2000 >200 >2000 v i latchup latchup performance above v cc and below gnd at 125 c (note 5.) 300 ma ja thermal resistance, junction to ambient soic package tssop 143 164 c/w 1. maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to th e recommended operating conditions. 2. tested to eia/jesd22a114a 3. tested to eia/jesd22a115a 4. tested to jesd22c101a 5. tested to eia/jesd78 recommended operating conditions symbol characteristics min max unit v cc dc supply voltage 4.5 5.5 v v in dc input voltage 0 5.5 v v out dc output voltage output in 3state high or low state 0 0 5.5 v cc v t a operating temperature range, all package types 55 125 c t r , t f input rise or fall time v cc = 5.0 v + 0.5 v 0 20 ns/v device junction temperature versus time to 0.1% bond failures junction temperature c time, hours time, years 80 1,032,200 117.8 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 1 1 10 100 1000 time, years normalized failure rate t j = 80 c t j = 90 c t j = 100 c t j = 110 c t j = 130 c t j = 120 c failure rate of plastic = ceramic until intermetallics occur figure 6. failure rate vs. time junction temperature
mc74vhct139a http://onsemi.com 4 dc characteristics (voltages referenced to gnd) v cc t a = 25 c t a 85 c t a = 55 to 125 c symbol parameter condition (v) min typ max min max min max unit v ih minimum highlevel input voltage 4.5 to 5.5 2 2 2 v v il maximum lowlevel input voltage 4.5 to 5.5 0.8 0.8 0.8 v v oh maximum highlevel output voltage v in = v ih or v il i oh = 50 m a 4.5 4.4 4.5 4.4 4.4 v ou u o age v in = v ih or v il i oh = 8 ma 4.5 3.94 3.8 3.66 v ol maximum lowlevel output voltage v in = v ih or v il i ol = 50 m a 4.5 0 0.1 0.1 0.1 v ou u o age v in = v ih or v il i oh = 8 ma 4.5 0.36 0.44 0.52 i in input leakage current v in = 5.5 v or gnd 0 to 5.5 0.1 1.0 1.0 m a i cc maximum quiescent supply current v in = v cc or gnd 5.5 4.0 40.0 40.0 m a i cct additional quiescent supply current (per pin) any one input: v in = 3.4 v all other inputs: v in = v cc or gnd 5.5 1.35 1.5 1.5 m a i opd output leakage current v out = 5.5 v 0 0.5 5 5 m a ?????????????????????????????????? ?????????????????????????????????? ac electrical characteristics (input t r = t f = 3.0ns) ???? ? ?? ? ???? ?????? ? ???? ? ?????? ????????? ? ??????? ? ????????? ???????? ? ?????? ? ???????? t a = 25 c ????? ? ??? ? ????? t a 85 c ????? ? ??? ? ????? t a = 55 to 125 c ??? ? ? ? ??? ???? ???? symbol ?????? ?????? parameter ????????? ????????? test conditions ??? ??? min ??? ??? typ ??? ??? max ??? ??? min ??? ??? max ??? ??? min ??? ??? max ??? ??? unit ???? ? ?? ? ???? t plh , t phl ?????? ? ???? ? ?????? maximum propagation delay, atoy ????????? ? ??????? ? ????????? v cc = 3.3 0.3 v c l = 15 pf c l = 50 pf ??? ? ? ? ??? ??? ? ?? ??? 7.2 9.7 ??? ?? ? ??? 11.0 14.5 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 13.0 16.5 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 13.0 16.5 ??? ? ? ? ??? ns ???? ???? ?????? ?????? a to y ????????? ????????? v cc = 5.0 0.5 v c l = 15 pf c l = 50 pf ??? ??? ??? ??? 5.0 6.5 ??? ??? 7.2 9.2 ??? ??? 1.0 1.0 ??? ??? 8.5 10.5 ??? ??? 1.0 1.0 ??? ??? 8.5 10.5 ??? ??? ???? ? ?? ? ???? t plh , t phl ?????? ? ???? ? ?????? maximum propagation delay, e to y ????????? ? ??????? ? ????????? v cc = 3.3 0.3 v c l = 15 pf c l = 50 pf ??? ? ? ? ??? ??? ? ?? ??? 6.4 8.9 ??? ?? ? ??? 9.2 12.7 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 11.0 14.5 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 11.0 14.5 ??? ? ? ? ??? ns ???? ? ?? ? ???? ?????? ? ???? ? ?????? e to y ????????? ? ??????? ? ????????? v cc = 5.0 0.5 v c l = 15 pf c l = 50 pf ??? ? ? ? ??? ??? ? ?? ??? 4.4 5.9 ??? ?? ? ??? 6.3 8.3 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 7.5 9.5 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 7.5 9.5 ??? ? ? ? ??? ???? ???? c in ?????? ?????? maximum input capacitance ????????? ????????? ??? ??? ??? ??? 4 ??? ??? 10 ??? ??? ??? ??? 10 ??? ??? ??? ??? 10 ??? ??? pf typical @ 25 c, v cc = 5.0v c pd power dissipation capacitance (note 6.) 26 pf 6. c pd is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption with out load. average operating current can be obtained by the equation: i cc(opr ) = c pd v cc f in + i cc /2 (per decoder). c pd is used to determine the noload dynamic power consumption; p d = c pd v cc 2 f in + i cc v cc .
mc74vhct139a http://onsemi.com 5 figure 7. switching waveform 1.5 v t phl t plh 3.0 v gnd y 1.5 v a 3.0 v gnd t phl t plh y e 1.5 v 1.5 v figure 8. switching waveform *includes all probe and jig capacitance figure 9. test circuit c l * test point device under test output v ol v oh v ol v oh
mc74vhct139a http://onsemi.com 6 package dimensions 0.25 (0.010) t b a m s s min min max max millimeters inches dim a b c d f g j k m p r 9.80 3.80 1.35 0.35 0.40 0.19 0.10 0 5.80 0.25 10.00 4.00 1.75 0.49 1.25 0.25 0.25 7 6.20 0.50 0.386 0.150 0.054 0.014 0.016 0.008 0.004 0 0.229 0.010 0.393 0.157 0.068 0.019 0.049 0.009 0.009 7 0.244 0.019 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 1 8 9 16 a b d 16pl k c g t seating plane r x 45 m j f p 8 pl 0.25 (0.010) b m m soic16 d suffix case 751b05 issue j tssop16 dt suffix case 948f01 issue o ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash o r gate burrs shall not exceed 0.15 (0.006) pe r side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusio n shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. section nn seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 16x ref k n n
mc74vhct139a http://onsemi.com 7 package dimensions soic eiaj16 m suffix case 96601 issue o h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z
mc74vhct139a http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 13036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc74vhct139a/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland
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